1. Field of the Invention
The present invention relates to the field of turbo coding, and more particularly, a low power operation of address interleaving in the turbo coding process.
2. Description of Related Art
Turbo coding is one of the most important components for data transmission in the third generation (3G) wireless standards such as the Universal mobile telephone standard (UMTS). Turbo coding provides forward error correction with exceptional coding gain, and provides for almost error-free data transmissions for all but the lowest signal-to-noise ratio (SNR) environments. The key component of the turbo coding structure is the interleaver which permutes the data sequence between the two constituent decoders. Research has shown that the overall performance of turbo codes are directly related to the “randomness” of the interleaver between the blocks.
The 3GPP standard defines the interleaver for turbo codes as a function based on the block sizes in the range of 40 to 5114 bits. The 3GPP interleaver uses a basic block interleaver structure with a complex inter-row and intra-row permutation to generate a pseudo-random interleaving pattern. While these permutations provide excellent algorithmic performance, they severely complicate the hardware implementation of the interleaver.
One possible architecture for a hardware address interleaver is to use a large memory which contains the entire address interleaving sequence. Thus the turbo components simply access the memory to retrieve the next interleaved address. This is the most straightforward implementation, but the entire table must be recalculated when the block size changes. While the overhead in loading the table may be acceptable for a mobile terminal, infrastructure turbo decoders may need to deal with multiple block sizes, one right after another.
An alternative to using a large memory based hardware address interleaver in a turbo decoder, is to generate an interleaved address on the fly. However, when an invalid address is generated, a discontinuous stream of interleaved addresses is created. Namely, there will be a cycle of operation in which no valid address is generated.